芯片制造中的化学镀技术研究进展

doi:10.6023/A22080347

摘要/Abstract

芯片制造中大量使用物理气相沉积、化学气相沉积、电镀、热压键合等技术来实现芯片导电互连. 与这些技术相比, 化学镀因具有均镀保形能力强、工艺条件温和、设备成本低、操作简单等优点, 被人们期望应用于芯片制造中, 从而在近年来得到大量的研究. 本综述首先简介了芯片制造中导电互连包括芯片内互连、芯片3D封装硅通孔(TSV)、重布线层、凸点、键合、封装载板孔金属化等制程中传统制造技术与化学镀技术的对比, 说明了化学镀用于芯片制造中的优势; 然后总结了芯片化学镀的原理与种类、接枝与活化前处理方法和关键材料; 并详细介绍了芯片内互连和TSV互连化学镀阻挡层、种子层、互连孔填充、化学镀凸点、再布线层、封装载板孔互连种子层以及凸点间键合的研究进展; 且讨论了化学镀液组成及作用, 超级化学镀填孔添加剂及机理等. 最后对化学镀技术未来应用于新一代芯片制造中进行了展望.

关键词: 芯片导电互连, 3D封装硅通孔, 阻挡层, 种子层, 凸点, 键合

As an indispensable part of today's society, the research on the manufacturing and packaging process of chips is particularly important. In the conventional chip manufacturing and packaging process, physical vapor deposition, chemical vapor deposition, electroplating, hot pressing and other processes are widely used. These processes are not only complicated and expensive, but also have some disadvantages that hinder the development of chip technology. The electroless deposition process has the advantages of mild conditions, low equipment cost, simple steps, and strong conformal ability. Researchers have paid attention to and studied its application in the field of chip manufacturing and packaging. Firstly, the principle and types of chip electroless deposition, activation, pre-grafting treatment methods and key materials were introduced in this paper. Secondly, to illustrate the advantages of electroless deposition in chip manufacturing, the main process of conductive interconnection in chip manufacturing were introduced, the conventional manufacturing process and electroless deposition manufacturing process in the interconnection process in chip, 3D packaging through silicon via (TSV) process, redistribution layer, bump, and bonding process were compared. Thirdly, the research progress of electroless deposition using in in-chip including barrier layer, seed layer, gap filling, substrate, bump is summarized and discussed; the composition and function of the plating solution, mechanism of additives in super electroless deposition gap filling are also discussed. Finally, the future application of electroless plating technology in the new generation of chip manufacturing is prospected.

Key words: chip electrical interconnection, 3D packaging through silicon via, barrier layer, seed layer, bump, bonding

引用此文

叶淳懿, 邬学贤, 张志彬, 丁萍, 骆静利, 符显珠. 芯片制造中的化学镀技术研究进展[J]. 化学学报, 2022, 80(12): 1643-1663.

Chunyi Ye, Xuexian Wu, Zhibin Zhang, Ping Ding, Jing-Li Luo, Xian-Zhu Fu. Research Progress of Electroless Plating Technology in Chip Manufacturing[J]. Acta Chimica Sinica, 2022, 80(12): 1643-1663.

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图/表 29

图1. 芯片导连互连结构及化学镀在芯片制程中主要应用的示意图

Figure 1. Schematic diagram of chip electric interconnection structure and the applications of electroless deposition in chip manufacturing

图2. 化学镀铜原理示意图

Figure 2. Schematic diagram of electroless copper deposition mechanism

ELD metal	Reaction	Application in chip manufacturing
Cu	Cu²⁺+2HCHO+4OH^‒→ Cu⁰+2HCOO^‒+2H₂O+H₂	Seed layer, gap filling, bump
Ni	Ni²⁺+2H₂O+2H₂PO₂^‒→Ni⁰+4H⁺+2HPO₃^2‒+H₂	Barrier layer, activator layer, UBM
Au	Au(SO₃)₂^3‒+e^‒+H₂O→SO₃^2‒+SO₂+Au+2OH^‒	Bump, UBM
Co	Co²⁺+2H₂O+2H₂PO₂^‒→Co⁰+4H⁺+2HPO₃^2‒+H₂	Barrier layer, gap filling
Pd	Pd²⁺+2H₂O+2H₂PO₂^‒→Pd⁰+4H⁺+2HPO₃^2‒+H₂	UBM

表1. 芯片制造中常见化学镀种类

Table 1. Common types of electroless deposition (ELD) in chip manufacturing

图3. (a)使用ETAS-SAM作为粘合剂的硅金属化工艺流程示意图; (b)在不同温度退火处理之前和之后沉积在Si衬底上铜膜的黏附强度[25]; 直接Sn/Pd胶体活化与使用SAM捕获(c)Pd纳米颗粒催化剂和(d) Au纳米颗粒催化剂的SEM图像[26-27]

Figure 3. (a) Process diagram of silicon metallization using ETAS-SAM; (b) adhesion strength of copper films deposited on Si substrates before and after annealing at different temperatures[25]; substrate SEM images of Sn/Pd colloid activation and using SAM absorb (c) Pd nanoparticle catalyst and (d) Au nanoparticle catalyst[26-27]

Molecular name	Abbreviations	Head group	References
3-Aminopropyltriethoxysilane	APTES/Am1	—NH₂	[26,28]
Aminopropyltrimethoxysilane	APTMS/APS	—NH₂	[29]
n-(2-Aminoethyl)-3-aminopropyl-trimethoxysilane	AEAPTMS/Am2	—NH₂	[23]
2-(Trimethoxysilyl)-ethylpyridine	Py	—C₅H₄N	[28]
N-(3-Trimethoxysilylpropyl) diethylenetriamine	TPDA	—NH₂	[24]
Alkyl(octadecyltrichlorosilane)	OTS	—CH₃	[22]
3-[2-(2-Aminoethylamino)ethylamino]-propyltrimethoxysilane	ETAS	—NH₂	[25]
(3-Mercaptopropyl)trimethoxysilane	MPTMS	—SH	[30]

表2. 芯片化学镀工艺中常用的接枝剂

Table 2. Grafting agents commonly used in chip electroless plating process

图4. (a)仅Pd活化与(b) Sn敏化Pd活化后的SEM与AFM图像[36]

Figure 4. SEM and AFM images of (a) Pd activation and (b) Sn sensitized and Pd activation[36]

图5. (a) APTMS-SAM捕获AuNP作为催化剂的SEM图像及AuNP粒径分布图[24]; (b) APTES-SAM捕获PdNP作为催化剂俯视及截面SEM图像[26]; (c)使用声化学法活化Ta基底并化学镀流程图与活化后基底表面形貌图[43]

Figure 5. (a) SEM images and particle size distribution of AuNP captured by APTMS-SAM[24]; (b) overlooking and cross sectional SEM images of PdNP captured by APTES-SAM[26]; (c) process diagram of ELD with Ta substrate activated by sonochemical and surface morphology of the activated substrate[43]

Activator	Process	References
PdCl₂	Absorb, reduce	[23,36]
Ni(NO₃)₂	Absorb, reduce	[29]
Pd	Absorb	[26]
Au	Absorb	[27]
Pd Layer	ICB	[42]
K₂PdCl₆	Sonochemical reduce	[43]
Cu Film	Sputter	[44]
Ru Layer	ALD	[45]
NiB Layer	ELD	[46]

表3. 芯片化学镀中常见活化剂

Table 3. Activators in chip electroless plating process

图6. 双大马士革工艺流程示意图

Figure 6. Schematic diagram of dual Damascus process

图7. (a) PVD沉积不均匀种子层示意图; (b)化学镀沉积均匀种子层示意图; (c)化学镀自下而上填充示意图

Figure 7. (a) Schematic diagram of uneven seed layer deposition by PVD; (b) schematic diagram of uniform seed layer deposited by electroless plating; (c) schematic diagram of bottom-up filling by electroless plating

图8. (a)在沟槽上化学镀的CoWP/NiB横截面TEM图像; (b)超级化学镀铜填充沟槽的横截面TEM图像[46]

Figure 8. (a) Cross-sectional TEM image of the electroless CoWP/NiB barrier layer deposited on the trench-patterned substrate; (b) cross-sectional TEM image of the trench deposited by super ELD[46]

图9. TSV制作流程示意图

Figure 9. TSV production process diagram

图10. (a)化学镀全湿工艺制作TSV示意图; (b)在TSV侧壁上吸附Pd纳米颗粒后的横截面及局部放大SEM图像; (c)化学镀Co-W-B阻挡层的横截面及局部放大SEM图像; (d)一次超级镀铜后TSV横截面SEM图像; (e)二次超级镀铜后TSV横截面SEM图像[53-54]

Figure 10. (a) Process flow of TSV metallization using ELD; (b) cross section and local magnified SEM images of Pd nanoparticles adsorbed on the side wall of TSV; (c) cross section and local magnified SEM images of Co-W-B barrier layer deposited by ELD; (d) cross section SEM image of TSV after first super ELD Cu; (e) cross section SEM image of TSV after second super ELD Cu[53-54]

图11. (a)典型RDL结构示意图[55]; (b)晶圆上化学镀镍后镀铜图像及局部放大横截面SEM图像[56]; (c)在Cu UBM上化学镀Ni-Au层并放置焊料结构示意图及RDL、RDL横截面SEM图像[55]

Figure 11. (a) Schematic of a typical RDL structure[55]; (b) digital and local magnified SEM image of ELD Ni/Cu on wafer[56]; (c) schematic diagram of ELD Ni-Au layer and placing solder on Cu UBM, and SEM images of RDL[55]

图12. (a) NiB阻挡层横截面及局部放大SEM图像[27]; (b) NiB阻挡层横截面及局部放大扫描离子显微镜(SIM)图像, 与晶圆上Ni-B电阻率图[39]. (c) PMAA上化学镀Ni阻挡层流程图, 与旋涂、改性、化学镀后表面及截面SEM图像[68]; (d) 化学镀NiPB厚度-时间图及化学镀不同时间后TSV截面SEM图像[23]; (e) 400 ℃退火后TSV横截面SEM图像与EDX元素分布[70]

Figure 12. (a) Cross section and local magnified SEM images of NiB barrier layer[27]; (b) cross section and local magnified SIM images of NiB barrier layer, and the Ni-B resistivity image on the wafer[39]; (c) process diagram of ELD Ni barrier layer on PMAA, surface and cross section SEM images of substrate after spin coating, modification and electroless plating[68]; (d) thickness-time diagram of NiPB and cross section SEM images of TSV after different time of electroless plating[23]; (e) cross section SEM images and EDX element distribution of TSV after annealing at 400 ℃[70]

图13. (a)在SiO2上两步制造NiReP阻挡层示意图; (b) NiReP、NiP 薄膜的薄层电阻随退火温度的变化[28]; (c)沟槽上化学镀NiB阻挡层的 SEM图像; (d) 400 ℃退火30 min后阻挡层的二次离子质谱(SIMS) 图[71]

Figure 13. (a) Schematic of two step fabrication of NiReP barrier layer on SiO2; (b) the variation of sheet resistance of NiReP and NiP films with annealing temperature[28]; (c) SEM images of ELD NiB barrier layer on trench; (d) the SIMS depth profiles of NiB samples after annealing up to 400 ℃ for 30 min[71]

Source of metal	Reducing agent	Additives	pH	Temperature/℃	References
NiSO₄•6H₂O (NH₄)₂ReO₄	NaH₂PO₂•H₂O	Sodium citrate	9.0 (adjusted with NaOH)	90	[28]
NiSO₄	DMAB	Citric acid monohydrate	9.0 (adjusted with TMAH)	70	[71]
NiSO₄•7H₂O Na₂MoO₄•6H₂O	NaH₂PO₂	C₆H₅Na₃O₇•H₂O SDS	9~10	85~90	[69]
Nickel chloride	Sodium hypophosphite Sodium borohydride	Ammonium citrate dibasic Ethylenediamine Sodium dodecyl sulfate Saccharine	13 (adjusted with NaOH)	65	[23]
Nickel sulfate	DMAB	Citric acid SPS	9.5	70	[27]
NiSO₄•6H₂O	DMAB	C₆H₅Na₃O₇•2H₂O	9	65	[66]
NiSO₄•6H₂O	NaH₂PO₂•H₂O	C₆H₅Na₃O₇•3H₂O	5.5 (adjusted with NH₃•H₂O)	80	[68]
NiSO₄•6H₂O Na₂WO₄•2H₂O	NaH₂PO₂•H₂O	Na₃C₆H₈O₇•2H₂O	7.0~9.0	80~95	[72]

表4. 芯片中化学镀镍基阻挡层镀液配方

Table 4. Formulation of electroless nickel-base barrier deposition bath for chip

图14. (a) NiB与CoB的SEM图像与不同温度退火后的电阻[73]; (b) Cu/Co-W-B界面横截面TEM图像与SIMS剖面数据[40]; (c) TiN/Cu/CoB/Si与TiN/Cu/CoWB/Si在400 ℃退火后的SIMS数据[76]; (d) PVD沉积Cu/Ta与化学镀沉积Cu/CoWB黏附强度数据; 电镀铜层、化学镀铜层及PVD铜层的电阻数据; 化学镀CoWB阻挡层与Cu种子层的30 mm晶圆图片; TSV内化学镀CoWB阻挡层与Cu种子层截面SEM图像[78]; (e) TSV横截面荧光显微镜图像; CoReP阻挡层表面与横截面SEM图像[79]

Figure 14. (a) SEM images of NiB and CoB, and resistance after annealing at different temperatures[73]; (b) cross section TEM images of Cu/Co-W-B and SIMS profile data[40]; (c) SIMS data of TiN/Cu/CoB/Si and TiN/Cu/CoWB/Si annealed at 400 ℃[76]; (d) adhesion strength of Cu/Ta deposited by PVD and Cu/CoWB deposited by electroless deposition; resistance data of electroplating copper layer, ELD copper layer and PVD copper layer; images of 30 mm wafer with ELD CoWB barrier layer and Cu seed layer; cross section SEM images of ELD CoWB barrier layer and Cu seed layer in TSV[78]; (e) cross section fluorescence microscope image of TSV; surface and cross section SEM images of CoReP barrier layer[79]

Source of metal	Reducing agent	Additives	pH	Temperature/℃	References
CoSO₄•6H₂O Na₂MoO₄•2H₂O	NaH₂PO₂	Na-citrate RE610 H₃BO₃	8.9~9.0 (adjusted with KOH)	—	[80]
CoSO₄•7H₂O Na₂WO₄•2H₂O	NaH₂PO₂•H₂O	Na₃C₆H₅O₇•2H₂O H₃BO₃	9 (adjusted with KOH)	85	[46]
CoSO₄•7H₂O Na₂WO₄	DMAB NaH₂PO₂	Na₃C₆H₅O₇•2H₂O RE610 HCl	9.5~9.7 (adjusted with NaOH)	20~85	[86]
CoCl₂•6H₂O Na₂WO₄•2H₂O	DMAB	H₃C₆H₅O₇•H₂O	9.5 (adjusted with TMAH)	75	[84-85]
CoSO₄•7H₂O Na₂WO₄•2H₂O	NaH₂PO₂	3Na-citrate H₃BO₃	8~12	90	[83]
Cobalt sulfate Tungsten acid	DMAB	Citric acid	9.5 (adjusted with TMAH)	70	[26]
Cobalt sulfate Tungsten acid	DMAB	Citric acid SPS	9.5	60	[40]
Cobalt sulfate	DMAB	Citric acid	9.5	70	[41,73]

表5. 芯片中化学镀钴基阻挡层镀液配方

Table 5. Formulation of electroless cobalt-base barrier deposition bath for chip

图15. (a)化学镀CoWP阻挡层表面SEM图像与截面TEM图像[46]; (b)化学镀CoP阻挡层表面及截面SEM图像[81]; (c)在铜互连线表面Pd活化化学镀覆盖层流程示意图; (d)化学镀CoWP覆盖层表面SEM图像及截面TEM图像[82]; (e)化学镀CoWB覆盖层表面及截面SEM图像[84]

Figure 15. (a) Surface SEM image and cross section TEM image of ELD CoWP barrier[46]; (b) surface and cross section SEM images of ELD CoP barrier[81]; (c) schematic diagram of electroless depositing capping layer with Pd activation on copper interconnection; (d) surface SEM image and cross section TEM image of ELD CoWP capping layer[82]; (e) surface and cross section SEM images of ELD CoWB capping layer[84]

Source of metal	Reducing agent	Additives	pH	Temperature/℃	References
CuSO₄•5H₂O	Paraformaldehyde	EDTA	— (adjusted with KOH)	70	[37]
CuSO₄•5H₂O	Glyoxylic acid	EDTA Surfactant RE-610	12.3~12.7 (adjusted with KOH)	65~75	[92]
CuSO₄•5H₂O	HCHO	KNaC₄H₄O₆•4H₂O 2,2'-dipyridyl Na₂S₂O₃•5H₂O NiCl₂•6H₂O	12~14 (adjusted with NaOH and Na₂CO₃)	25	[95]
CuSO₄•5H₂O	Glyoxylic acid	EDTA 2,2'-dipyridine PEG	12.7 (adjusted with TMAH)	60 or 70	[101]
CuSO₄•5H₂O	HCHO	EDTA PEG	12.6~12.7 (adjusted with NaOH)	45	[96]
CuSO₄•5H₂O MnSO₄•H₂O	HCHO	C₄H₄KNaO₆•4H₂O	13 (adjusted with NaOH)	—	[89]
CuSO₄•5H₂O	Glyoxylic acid	EDTA PEG-Thiol	12.5	70	[45,97⇓⇓ -100]

表6. 芯片中化学镀铜种子层镀液配方

Table 6. Formulation of electroless copper seed layer deposition bath for chip

图16. (a1)经过敏化-活化后的Ta基底表面与化学镀铜后截面SEM图像; (a2)在PVD制备铜种子层和化学镀铜种子层上电沉积铜膜后横截面SEM图像; (a3)铜种子层TEM图像; (a4)在不同线宽沟道上使用PVD和化学镀工艺覆盖铜种子层的横截面SEM图像; (a5)在不同线宽的沟道上以化学镀铜为种子层电镀不同时间时的横截面SEM图像[21]; (b1) DMAB氧化峰电流密度与Pd颗粒密度的关系; (b2) DMAB氧化峰电流密度与Pd颗粒总面积的关系[77]; (c1)在SAM上生长的催化剂颗粒TEM图像; (c2)催化剂结合在SAM上的横截面TEM图像[78]; (d1)经过SAM功能化后化学镀铜20 s的SEM图像; (d2)未经SAM功能化化学镀铜20 s的SEM图像[11]; (e1)在硅基底上(含ETAS分子层)化学镀铜种子层并退火后TEM图像; (e2)在硅基底上(不含ETAS分子层)化学镀铜种子层并退火后SEM图像[14]

Figure 16. (a1) Surface SEM image of Ta substrate after sensitization-activation and cross section SEM image after electroless copper deposition; (a2) cross section SEM images of electroplating copper film after depositing copper seed layer by PVD or ELD; (a3) TEM image of copper seed layer; (a4) cross section SEM images of copper seed layer deposited by PVD or ELD on different width trench; (a5) cross section SEM images of electroplating for different time using ELD copper as seed layer on different width trench[21]; (b1) relationship between oxidation peak current density of DMAB and Pd particle density; (b2) relationship between oxidation peak current density of DMAB and total area of Pd particles[77]; (c1) TEM image of catalyst particles grown on SAM; (c2) cross section TEM image of the catalyst bonded on SAM[78]; (d1) SEM image of electroless copper depositing 20 s after SAM functionalization; (d2) SEM image of electroless copper depositing 20 s without SAM functionalization[11]; (e1) TEM image of silicon substrate (including ETAS molecular layer) with ELD and annealing; (e2) TEM image of silicon substrate (without ETAS molecular layer) with ELD and annealing[14]

图17. (a) TSV内Ti/Co阻挡层上化学镀Cu种子层截面TEM图像与能量过滤TEM图像[99]; (b) TSV底部ALD-Ru上化学镀Cu种子层TEM图像与EDS图谱[106]; (c) Ta上化学镀Ru/Cu的TEM图像与EDS线扫描图谱[96]

Figure 17. (a) Cross section TEM images and energy filtering TEM images of ELD Cu seed layer on Ti/Co barrier layer in TSV[99]; (b) TEM image and EDS spectra of ELD Cu seed layer on ALD-Ru at the bottom of TSV[106]; (c) TEM image and EDS line scanning map of ELD Ru/Cu on Ta[96]

图18. (a) SAP与mSAP工艺流程图; (b) SAP种子层图像[110]; (c) SAF工艺示意图; (d) SAF种子层图像; (e)化学镀40 min孔图像[112]

Figure 18. (a) Process diagram of SAP and mSAP; (b) image of SAP seed layer[110]; (c) diagram of SAF; (d) image of SAF seed layer; (e) image of ELD for 40 min[112]

图19. (a)单添加剂体系超级化学镀机理示意图; (b)双添加剂体系超级化学镀机理示意图

Figure 19. (a) Mechanism of super ELD using single additive system; (b) mechanism of super ELD using double additives system

图20. (a) 30 nm线宽超级化学镀填孔[95]; (b)含SAM活化步骤的超级化学镀铜横截面SEM图像[134]; (c) V0级W上化学填充Co的TEM图像与电子能量损失谱; (d) M1、M2级间化学填充Co示意图与TEM图像[137]

Figure 20. (a) Super ELD gap-fill for 30 nm width[95]; (b) cross section SEM images of super ELD with SAM activation[134]; (c) TEM image and electron energy loss spectra of ELD filled Co on V0 level W; (d) schematic diagram and TEM image of ELD fill Co between M1 level and M2 level[137]

图21. (a)化学镀铜填充TSV后的横截面聚焦离子束(FIB)-SIM图像及局部放大图[139]; (b) PVD-WNi作为阻挡/活化层化学镀铜填充TSV横截面SEM图像及局部放大图[140]; (c)电镀与化学镀填充TSV并形成背凸流程图; 化学镀填充TSV并形成背凸SEM图像与局部放大图[141]; (d)使用TMV技术与晶圆转移技术连接MEMS与CMOS流程图; TMV SEM图像[142]; (e1)化学镀镍填充TSV SEM图像; (e2)化学镀镍填充TSV EDS谱图[143]

Figure 21. (a) Cross section and local magnified FIB-SIM images of TSV after ELD Cu fill[139]; (b) cross section and local magnified SEM images of ELD Cu fill using PVD-WNi as barrier and activator layer[140]; (c) process diagram of filling TSV and form back-bumps using electroplating or ELD; SEM and local magnified image of filling TSV and form back-bumps using ELD[141]; (d) process diagram of connecting MEMS and CMOS using TMV and wafer transfer technology; SEM image of TMV[142]; (e1) SEM images of TSV filled by ELD Ni; (e2) EDS spectra of TSV filled by ELD Ni[143]

图22. (a)化学镀金凸点阵列SEM图像与高度数据[58]; (b)化学镀金凸点阵列SEM图像; (c)金凸点不同退火温度下剪切强度图、高度分布直方图、XPS图谱[147]; (d)传统Cu/Sn凸点制造过程; (e)化学镀Cu/Sn凸点制造过程; (f)化学镀Cu凸点SEM图像; (g) Cu凸点上化学镀Sn SEM图像; (h)化学镀Cu/Sn凸点回流后SEM图像[148]

Figure 22. (a) SEM images and height data of ELD Au bumps array[58]; (b) SEM images of ELD Au bumps array; (c) shear strength diagram at different annealing temperatures, height distribution histogram and XPS diagram of Au bump[147]; (d) conventional manufacturing process of Cu/Sn bumps; (e) ELD manufacturing process of Cu/Sn bumps; (f) SEM image of ELD Cu bumps; (g) SEM image of ELD Sn on Cu bumps; (h) SEM image of ELD Cu/Sn bumps after reflowing[148]

图23. (a)化学镀铜键合铜柱生长模型与SEM图像; (b)两种失效方式模型与SEM图像[151]; (c) MELI流程与器件; (d)凸点阵列键合不均匀示意图与SEM图像; (e) MELI-Au键合铜柱SEM图像, (f), (g)为(e)中两对铜柱键合的放大图; (h)使用3种MELI工艺键合铜柱的SEM图片[7]

Figure 23. (a) Growth model and SEM images of ELD Cu bonded copper bumps; (b) two failure mode model and SEM images[151]; (c) MELI process and devices; (d) schematic diagram and SEM images of bumps array that bonded uneven; (e) SEM images of bonding Cu pillar using MELI-Au, (f) and (g) are local magnified of bonded bumps in (e); (h) SEM images of copper pillars bonded by MELI processes[7]

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