Research Progress of Electroless Plating Technology in Chip Manufacturing

doi:10.6023/A22080347

Abstract

As an indispensable part of today's society, the research on the manufacturing and packaging process of chips is particularly important. In the conventional chip manufacturing and packaging process, physical vapor deposition, chemical vapor deposition, electroplating, hot pressing and other processes are widely used. These processes are not only complicated and expensive, but also have some disadvantages that hinder the development of chip technology. The electroless deposition process has the advantages of mild conditions, low equipment cost, simple steps, and strong conformal ability. Researchers have paid attention to and studied its application in the field of chip manufacturing and packaging. Firstly, the principle and types of chip electroless deposition, activation, pre-grafting treatment methods and key materials were introduced in this paper. Secondly, to illustrate the advantages of electroless deposition in chip manufacturing, the main process of conductive interconnection in chip manufacturing were introduced, the conventional manufacturing process and electroless deposition manufacturing process in the interconnection process in chip, 3D packaging through silicon via (TSV) process, redistribution layer, bump, and bonding process were compared. Thirdly, the research progress of electroless deposition using in in-chip including barrier layer, seed layer, gap filling, substrate, bump is summarized and discussed; the composition and function of the plating solution, mechanism of additives in super electroless deposition gap filling are also discussed. Finally, the future application of electroless plating technology in the new generation of chip manufacturing is prospected.

Key words: chip electrical interconnection, 3D packaging through silicon via, barrier layer, seed layer, bump, bonding

Cite this article

Chunyi Ye, Xuexian Wu, Zhibin Zhang, Ping Ding, Jing-Li Luo, Xian-Zhu Fu. Research Progress of Electroless Plating Technology in Chip Manufacturing[J]. Acta Chimica Sinica, 2022, 80(12): 1643-1663.

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Fig. & Tab. 29

Figure 1. Schematic diagram of chip electric interconnection structure and the applications of electroless deposition in chip manufacturing

Figure 2. Schematic diagram of electroless copper deposition mechanism

ELD metal	Reaction	Application in chip manufacturing
Cu	Cu²⁺+2HCHO+4OH^‒→ Cu⁰+2HCOO^‒+2H₂O+H₂	Seed layer, gap filling, bump
Ni	Ni²⁺+2H₂O+2H₂PO₂^‒→Ni⁰+4H⁺+2HPO₃^2‒+H₂	Barrier layer, activator layer, UBM
Au	Au(SO₃)₂^3‒+e^‒+H₂O→SO₃^2‒+SO₂+Au+2OH^‒	Bump, UBM
Co	Co²⁺+2H₂O+2H₂PO₂^‒→Co⁰+4H⁺+2HPO₃^2‒+H₂	Barrier layer, gap filling
Pd	Pd²⁺+2H₂O+2H₂PO₂^‒→Pd⁰+4H⁺+2HPO₃^2‒+H₂	UBM

Table 1. Common types of electroless deposition (ELD) in chip manufacturing

Figure 3. (a) Process diagram of silicon metallization using ETAS-SAM; (b) adhesion strength of copper films deposited on Si substrates before and after annealing at different temperatures[25]; substrate SEM images of Sn/Pd colloid activation and using SAM absorb (c) Pd nanoparticle catalyst and (d) Au nanoparticle catalyst[26-27]

Molecular name	Abbreviations	Head group	References
3-Aminopropyltriethoxysilane	APTES/Am1	—NH₂	[26,28]
Aminopropyltrimethoxysilane	APTMS/APS	—NH₂	[29]
n-(2-Aminoethyl)-3-aminopropyl-trimethoxysilane	AEAPTMS/Am2	—NH₂	[23]
2-(Trimethoxysilyl)-ethylpyridine	Py	—C₅H₄N	[28]
N-(3-Trimethoxysilylpropyl) diethylenetriamine	TPDA	—NH₂	[24]
Alkyl(octadecyltrichlorosilane)	OTS	—CH₃	[22]
3-[2-(2-Aminoethylamino)ethylamino]-propyltrimethoxysilane	ETAS	—NH₂	[25]
(3-Mercaptopropyl)trimethoxysilane	MPTMS	—SH	[30]

Table 2. Grafting agents commonly used in chip electroless plating process

Figure 4. SEM and AFM images of (a) Pd activation and (b) Sn sensitized and Pd activation[36]

Figure 5. (a) SEM images and particle size distribution of AuNP captured by APTMS-SAM[24]; (b) overlooking and cross sectional SEM images of PdNP captured by APTES-SAM[26]; (c) process diagram of ELD with Ta substrate activated by sonochemical and surface morphology of the activated substrate[43]

Activator	Process	References
PdCl₂	Absorb, reduce	[23,36]
Ni(NO₃)₂	Absorb, reduce	[29]
Pd	Absorb	[26]
Au	Absorb	[27]
Pd Layer	ICB	[42]
K₂PdCl₆	Sonochemical reduce	[43]
Cu Film	Sputter	[44]
Ru Layer	ALD	[45]
NiB Layer	ELD	[46]

Table 3. Activators in chip electroless plating process

Figure 6. Schematic diagram of dual Damascus process

Figure 7. (a) Schematic diagram of uneven seed layer deposition by PVD; (b) schematic diagram of uniform seed layer deposited by electroless plating; (c) schematic diagram of bottom-up filling by electroless plating

Figure 8. (a) Cross-sectional TEM image of the electroless CoWP/NiB barrier layer deposited on the trench-patterned substrate; (b) cross-sectional TEM image of the trench deposited by super ELD[46]

Figure 9. TSV production process diagram

Figure 10. (a) Process flow of TSV metallization using ELD; (b) cross section and local magnified SEM images of Pd nanoparticles adsorbed on the side wall of TSV; (c) cross section and local magnified SEM images of Co-W-B barrier layer deposited by ELD; (d) cross section SEM image of TSV after first super ELD Cu; (e) cross section SEM image of TSV after second super ELD Cu[53-54]

Figure 11. (a) Schematic of a typical RDL structure[55]; (b) digital and local magnified SEM image of ELD Ni/Cu on wafer[56]; (c) schematic diagram of ELD Ni-Au layer and placing solder on Cu UBM, and SEM images of RDL[55]

Figure 12. (a) Cross section and local magnified SEM images of NiB barrier layer[27]; (b) cross section and local magnified SIM images of NiB barrier layer, and the Ni-B resistivity image on the wafer[39]; (c) process diagram of ELD Ni barrier layer on PMAA, surface and cross section SEM images of substrate after spin coating, modification and electroless plating[68]; (d) thickness-time diagram of NiPB and cross section SEM images of TSV after different time of electroless plating[23]; (e) cross section SEM images and EDX element distribution of TSV after annealing at 400 ℃[70]

Figure 13. (a) Schematic of two step fabrication of NiReP barrier layer on SiO2; (b) the variation of sheet resistance of NiReP and NiP films with annealing temperature[28]; (c) SEM images of ELD NiB barrier layer on trench; (d) the SIMS depth profiles of NiB samples after annealing up to 400 ℃ for 30 min[71]

Source of metal	Reducing agent	Additives	pH	Temperature/℃	References
NiSO₄•6H₂O (NH₄)₂ReO₄	NaH₂PO₂•H₂O	Sodium citrate	9.0 (adjusted with NaOH)	90	[28]
NiSO₄	DMAB	Citric acid monohydrate	9.0 (adjusted with TMAH)	70	[71]
NiSO₄•7H₂O Na₂MoO₄•6H₂O	NaH₂PO₂	C₆H₅Na₃O₇•H₂O SDS	9~10	85~90	[69]
Nickel chloride	Sodium hypophosphite Sodium borohydride	Ammonium citrate dibasic Ethylenediamine Sodium dodecyl sulfate Saccharine	13 (adjusted with NaOH)	65	[23]
Nickel sulfate	DMAB	Citric acid SPS	9.5	70	[27]
NiSO₄•6H₂O	DMAB	C₆H₅Na₃O₇•2H₂O	9	65	[66]
NiSO₄•6H₂O	NaH₂PO₂•H₂O	C₆H₅Na₃O₇•3H₂O	5.5 (adjusted with NH₃•H₂O)	80	[68]
NiSO₄•6H₂O Na₂WO₄•2H₂O	NaH₂PO₂•H₂O	Na₃C₆H₈O₇•2H₂O	7.0~9.0	80~95	[72]

Table 4. Formulation of electroless nickel-base barrier deposition bath for chip

Figure 14. (a) SEM images of NiB and CoB, and resistance after annealing at different temperatures[73]; (b) cross section TEM images of Cu/Co-W-B and SIMS profile data[40]; (c) SIMS data of TiN/Cu/CoB/Si and TiN/Cu/CoWB/Si annealed at 400 ℃[76]; (d) adhesion strength of Cu/Ta deposited by PVD and Cu/CoWB deposited by electroless deposition; resistance data of electroplating copper layer, ELD copper layer and PVD copper layer; images of 30 mm wafer with ELD CoWB barrier layer and Cu seed layer; cross section SEM images of ELD CoWB barrier layer and Cu seed layer in TSV[78]; (e) cross section fluorescence microscope image of TSV; surface and cross section SEM images of CoReP barrier layer[79]

Source of metal	Reducing agent	Additives	pH	Temperature/℃	References
CoSO₄•6H₂O Na₂MoO₄•2H₂O	NaH₂PO₂	Na-citrate RE610 H₃BO₃	8.9~9.0 (adjusted with KOH)	—	[80]
CoSO₄•7H₂O Na₂WO₄•2H₂O	NaH₂PO₂•H₂O	Na₃C₆H₅O₇•2H₂O H₃BO₃	9 (adjusted with KOH)	85	[46]
CoSO₄•7H₂O Na₂WO₄	DMAB NaH₂PO₂	Na₃C₆H₅O₇•2H₂O RE610 HCl	9.5~9.7 (adjusted with NaOH)	20~85	[86]
CoCl₂•6H₂O Na₂WO₄•2H₂O	DMAB	H₃C₆H₅O₇•H₂O	9.5 (adjusted with TMAH)	75	[84-85]
CoSO₄•7H₂O Na₂WO₄•2H₂O	NaH₂PO₂	3Na-citrate H₃BO₃	8~12	90	[83]
Cobalt sulfate Tungsten acid	DMAB	Citric acid	9.5 (adjusted with TMAH)	70	[26]
Cobalt sulfate Tungsten acid	DMAB	Citric acid SPS	9.5	60	[40]
Cobalt sulfate	DMAB	Citric acid	9.5	70	[41,73]

Table 5. Formulation of electroless cobalt-base barrier deposition bath for chip

Figure 15. (a) Surface SEM image and cross section TEM image of ELD CoWP barrier[46]; (b) surface and cross section SEM images of ELD CoP barrier[81]; (c) schematic diagram of electroless depositing capping layer with Pd activation on copper interconnection; (d) surface SEM image and cross section TEM image of ELD CoWP capping layer[82]; (e) surface and cross section SEM images of ELD CoWB capping layer[84]

Source of metal	Reducing agent	Additives	pH	Temperature/℃	References
CuSO₄•5H₂O	Paraformaldehyde	EDTA	— (adjusted with KOH)	70	[37]
CuSO₄•5H₂O	Glyoxylic acid	EDTA Surfactant RE-610	12.3~12.7 (adjusted with KOH)	65~75	[92]
CuSO₄•5H₂O	HCHO	KNaC₄H₄O₆•4H₂O 2,2'-dipyridyl Na₂S₂O₃•5H₂O NiCl₂•6H₂O	12~14 (adjusted with NaOH and Na₂CO₃)	25	[95]
CuSO₄•5H₂O	Glyoxylic acid	EDTA 2,2'-dipyridine PEG	12.7 (adjusted with TMAH)	60 or 70	[101]
CuSO₄•5H₂O	HCHO	EDTA PEG	12.6~12.7 (adjusted with NaOH)	45	[96]
CuSO₄•5H₂O MnSO₄•H₂O	HCHO	C₄H₄KNaO₆•4H₂O	13 (adjusted with NaOH)	—	[89]
CuSO₄•5H₂O	Glyoxylic acid	EDTA PEG-Thiol	12.5	70	[45,97⇓⇓ -100]

Table 6. Formulation of electroless copper seed layer deposition bath for chip

Figure 16. (a1) Surface SEM image of Ta substrate after sensitization-activation and cross section SEM image after electroless copper deposition; (a2) cross section SEM images of electroplating copper film after depositing copper seed layer by PVD or ELD; (a3) TEM image of copper seed layer; (a4) cross section SEM images of copper seed layer deposited by PVD or ELD on different width trench; (a5) cross section SEM images of electroplating for different time using ELD copper as seed layer on different width trench[21]; (b1) relationship between oxidation peak current density of DMAB and Pd particle density; (b2) relationship between oxidation peak current density of DMAB and total area of Pd particles[77]; (c1) TEM image of catalyst particles grown on SAM; (c2) cross section TEM image of the catalyst bonded on SAM[78]; (d1) SEM image of electroless copper depositing 20 s after SAM functionalization; (d2) SEM image of electroless copper depositing 20 s without SAM functionalization[11]; (e1) TEM image of silicon substrate (including ETAS molecular layer) with ELD and annealing; (e2) TEM image of silicon substrate (without ETAS molecular layer) with ELD and annealing[14]

Figure 17. (a) Cross section TEM images and energy filtering TEM images of ELD Cu seed layer on Ti/Co barrier layer in TSV[99]; (b) TEM image and EDS spectra of ELD Cu seed layer on ALD-Ru at the bottom of TSV[106]; (c) TEM image and EDS line scanning map of ELD Ru/Cu on Ta[96]

Figure 18. (a) Process diagram of SAP and mSAP; (b) image of SAP seed layer[110]; (c) diagram of SAF; (d) image of SAF seed layer; (e) image of ELD for 40 min[112]

Figure 19. (a) Mechanism of super ELD using single additive system; (b) mechanism of super ELD using double additives system

Figure 20. (a) Super ELD gap-fill for 30 nm width[95]; (b) cross section SEM images of super ELD with SAM activation[134]; (c) TEM image and electron energy loss spectra of ELD filled Co on V0 level W; (d) schematic diagram and TEM image of ELD fill Co between M1 level and M2 level[137]

Figure 21. (a) Cross section and local magnified FIB-SIM images of TSV after ELD Cu fill[139]; (b) cross section and local magnified SEM images of ELD Cu fill using PVD-WNi as barrier and activator layer[140]; (c) process diagram of filling TSV and form back-bumps using electroplating or ELD; SEM and local magnified image of filling TSV and form back-bumps using ELD[141]; (d) process diagram of connecting MEMS and CMOS using TMV and wafer transfer technology; SEM image of TMV[142]; (e1) SEM images of TSV filled by ELD Ni; (e2) EDS spectra of TSV filled by ELD Ni[143]

Figure 22. (a) SEM images and height data of ELD Au bumps array[58]; (b) SEM images of ELD Au bumps array; (c) shear strength diagram at different annealing temperatures, height distribution histogram and XPS diagram of Au bump[147]; (d) conventional manufacturing process of Cu/Sn bumps; (e) ELD manufacturing process of Cu/Sn bumps; (f) SEM image of ELD Cu bumps; (g) SEM image of ELD Sn on Cu bumps; (h) SEM image of ELD Cu/Sn bumps after reflowing[148]

Figure 23. (a) Growth model and SEM images of ELD Cu bonded copper bumps; (b) two failure mode model and SEM images[151]; (c) MELI process and devices; (d) schematic diagram and SEM images of bumps array that bonded uneven; (e) SEM images of bonding Cu pillar using MELI-Au, (f) and (g) are local magnified of bonded bumps in (e); (h) SEM images of copper pillars bonded by MELI processes[7]

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