Acta Chimica Sinica ›› 2022, Vol. 80 ›› Issue (12): 1643-1663.DOI: 10.6023/A22080347 Previous Articles     Next Articles

Review

芯片制造中的化学镀技术研究进展

叶淳懿, 邬学贤, 张志彬, 丁萍, 骆静利, 符显珠*()   

  1. 深圳大学材料学院 深圳 518000
  • 投稿日期:2022-08-06 发布日期:2022-09-16
  • 通讯作者: 符显珠
  • 作者简介:

    叶淳懿, 深圳大学材料学院材料与化工专业在读硕士研究生, 研究方向为面向电子与能源领域应用的化学镀技术及其活化剂.

    符显珠, 深圳大学材料学院教授, 博士生导师, 从事电化学能源材料与器件及电子材料与制程研究. 2007年厦门大学化学系博士毕业, 2008~2012年在加拿大阿尔伯塔大学做博士后并到美国伯克利国家实验室进行访问研究, 曾于中国科学院深圳先进技术研究院工作. 近5年以通讯作者在Nature Catalysis、Journal of the American Chemical Society、Angewandte Chemie、Energy & Environmental Science、Science Bulletin(科学通报)等期刊发表SCI论文100多篇.

  • 基金资助:
    国家自然科学基金(21975163)

Research Progress of Electroless Plating Technology in Chip Manufacturing

Chunyi Ye, Xuexian Wu, Zhibin Zhang, Ping Ding, Jing-Li Luo, Xian-Zhu Fu()   

  1. College of Material Science and Engineering, Shenzhen University, Shenzhen 518000, China
  • Received:2022-08-06 Published:2022-09-16
  • Contact: Xian-Zhu Fu
  • Supported by:
    National Natural Science Foundation of China(21975163)

As an indispensable part of today's society, the research on the manufacturing and packaging process of chips is particularly important. In the conventional chip manufacturing and packaging process, physical vapor deposition, chemical vapor deposition, electroplating, hot pressing and other processes are widely used. These processes are not only complicated and expensive, but also have some disadvantages that hinder the development of chip technology. The electroless deposition process has the advantages of mild conditions, low equipment cost, simple steps, and strong conformal ability. Researchers have paid attention to and studied its application in the field of chip manufacturing and packaging. Firstly, the principle and types of chip electroless deposition, activation, pre-grafting treatment methods and key materials were introduced in this paper. Secondly, to illustrate the advantages of electroless deposition in chip manufacturing, the main process of conductive interconnection in chip manufacturing were introduced, the conventional manufacturing process and electroless deposition manufacturing process in the interconnection process in chip, 3D packaging through silicon via (TSV) process, redistribution layer, bump, and bonding process were compared. Thirdly, the research progress of electroless deposition using in in-chip including barrier layer, seed layer, gap filling, substrate, bump is summarized and discussed; the composition and function of the plating solution, mechanism of additives in super electroless deposition gap filling are also discussed. Finally, the future application of electroless plating technology in the new generation of chip manufacturing is prospected.

Key words: chip electrical interconnection, 3D packaging through silicon via, barrier layer, seed layer, bump, bonding